Electrical and physical limitations exist on the extent to which SiO2 gate dielectrics can be made thinner. These include gate leakage currents tunneling through the thin gate oxide, limitations on the ability to form very thin oxide films with uniform thickness, and the inability of very thin SiO2 gate dielectric layers to prevent dopant diffusion from the gate polysilicon into the underlying channel (“polysilicon depletion”). Accordingly, recent downscaling efforts have focused on high-k dielectric materials having dielectric constants greater than that of SiO2, which can be formed in a thicker layer than scaled SiO2, and yet which produce equivalent field effect performance. A thicker high-k dielectric layer can thus be formed to avoid or mitigate tunneling leakage currents, while still achieving the required electrical performance equivalent (e.g., capacitance value) of a thinner SiO2.
With the relatively thick gate dielectrics and gate contact structures of the past, the polysilicon depletion issue was not critical to ensuring desired device performance. However, as gate dielectrics and gate contacts continue to become smaller through scaling, the polysilicon depletion problem is more pronounced, wherein polysilicon depletion regions of 3 to 4 angstroms become a significant fraction of the overall effective gate capacitance. Thus, while polysilicon gate contacts have previously offered flexibility in providing dual work functions for CMOS processes, the future viability of conventional polysilicon gate technology is lessened as scaling efforts continue.
In addition, improving the control of short channel effects and enhancing performance are major challenges in scaling CMOS devices. For example, short channel effects can be mitigated by increasing gate capacitance. This implies the use of thinner gate dielectrics which require the introduction of high-k materials to overcome the exponential increase of direct tunneling through gate oxide. Accordingly, attention has recently been directed again to the possibility of using metal gate contacts in CMOS products, where the metal gate materials conceivably do not need doping for conductivity improvement. Although this approach presumably avoids polysilicon depletion issues with respect to gate capacitance, there remains a need for dual or differentiated work function capability (e.g., for pMOS and nMOS transistors) in CMOS processes. In this regard, metal work functions are not shifted as easily by the same amounts as was the case for polysilicon. In addition, transistors with high-k metal gates have degraded carrier mobility. Accordingly, there is a need for improved CMOS transistor gate designs and fabrication techniques by which the benefits of scaling can be achieved while avoiding or mitigating the degraded carrier mobility found in conventional devices.